The partnership was signed after the development of the CARM technology.
INESC-ID from Instituto Superior Técnico collaborates with Intel© since researchers Aleksandar Ilic, Leonel Sousa, and Frederico Pratas developed the fundamental Cache-Aware Roofline (CARM) models, which allow taking advantage of several processor features. For example, it helps to visualize the processing limit, thus helping optimize performance and energy consumption.
The CARM technology allows programmers to understand the limitations of their source code given the computer architecture in use. The model enables users to verify if they are taking advantage of the full processor capabilities, leading to optimal codes and energy consumption. “This model can be used in any processor. So far, it is used to characterize any Intel processor, from laptops to the ones used in supercomputers,” said Prof. Leonel Sousa, one of the project leaders.
The idea arose after the researchers made a thorough study about other models with similar goals “but had limitations that prevented practical uses outside the academy,” explains Professor Sousa. “We worked for four years on this model, research that was done at INESC-ID, with grants from several projects, and resulted in a doctoral dissertation.”
The CARM model was integrated into the Parallel Studio XE, the leading framework for code development, in 2017. Since then, the researchers have worked on extending the model, e.g., to GPUs, and on making it aware of the requirements of the application. They are currently involved in exploring the model for accelerators based on the RISC V, in the scope of the European Processing Initiative (EPI), and for maximizing the performance and energy efficiency of sparse computations on emerging HPC systems, in the SparCity project, both in the context of The European High Performance Computing Joint Undertaking (EuroHPC JU).